In the semiconductor industry over the course of the past several years, there has emerged a trend toward the development of lower voltage, submicron processing technologies. For example, it is increasingly common to find semiconductor products that operate with supply voltages of 3.3 volts, rather than the traditional 5 volt levels. Problems arise, however, with building low voltage products which are to be compatible with existing products that utilize a higher power supply potential. One problem exists with the compatibility of conventional I/O buffers using CMOS low-voltage processing technology. If conventional output buffers are used in CMOS products operating with a low voltage supply, then current leakage problems may arise when higher voltages are driven into the output pad while the buffer is in a tristate mode. Obviously, current leakage problems are undesirable in an integrated circuit, especially in cases where the magnitude of the leakage violates accepted I/O bus standards.
Other problems also exist when tristateable output buffers operating from a low voltage supply are connected to a higher voltage bus. In addition to the leakage problem mentioned above, there are two long-term reliability issues to consider. These problems are commonly referred to as "hot electron reliability" and "p-device stability".
Hot electron reliability denotes the phenomenon wherein the operating performance of a transistor degrades due to a build up of trapped carriers in the gate oxide region. Because electron carriers have a higher mobility than hole carriers, this problem is more pronounced for n-channel devices as compared to p-channel devices.
The performance of a transistor degrades as the electric field of the trapped carriers interact with the electric field applied at the gate of the transistor. Hot electron reliability is a probabilistic model where the probability of a carrier being trapped in the oxide is a function of the energy of the carrier as it passes through the channel of the transistor. At the operating point of saturation, devices have the highest probability of injecting carriers into the gate oxide. Among the factors that determine if a transistor will experience hot electron reliability problems include: frequency of switching, size of load, operating temperature, driving potential, device channel length, device channel width, the rise/fall times of the signal on the gate, and the expected lifetime of operation of the transistor in the field.
Another long-term reliability risk, referred to as p-device stability, involves the undesirable shift in the threshold voltage when excessive electric fields have been applied across the gate oxide of a p-channel transistor. Note that n-channel devices are also susceptible to a shift in their threshold voltage as a result of excessive electric fields being experienced across their gate oxide. However, p-channel devices, are usually more sensitive to this phenomena.
As will be seen, the present invention provides for a 5.0 volt tolerant output buffer ideally-suited for low voltage operation. The invented input/output buffer is compatible with CMOS processing technology while overcoming the aforementioned problems. Specifically, the present invention provides a tristateable CMOS output buffer that does not experience current leakage problems when supplied with 3.3 volts, and when 5 volts or higher is driven into the output pad while the buffer is tristated. The invented buffer circuit also addresses the problems associated with hot electron and p-device stability reliability requirements.